In semiconductor electronics, Dennard scaling, also known as MOSFET scaling, is a scaling law which states roughly that, as transistors get smaller, their power density stays constant, so that the power use stays in proportion with area; both voltage and current scale (downward) with length. The law, originally formulated for MOSFETs, is based on a 1974 paper co-authored by Robert H. Dennard, after whom it is named.
Derivation
Dennard's model of MOSFET scaling implies that, with every technology generation:
Transistor dimensions could be scaled by −30% (0.7×). This has the following effects simultaneously: The area of an individual device reduces by 50%, because area is length times width. The capacitance associated with the device, C, is reduced by 30% (0.7×), because capacitance varies with area over distance. To keep the electric field unchanged, the voltage, V, is reduced by 30% (0.7×), because voltage is field times length. Characteristics such as current and transition time are likewise scaled down by 30%, due to their relationship with capacitance and voltage. Overall circuit delay is assumed to be dominated by transition time, so it too is reduced by 30%. The above effects lead to an increase in operating frequency, f, by about 40% (1.4×), because frequency varies with one over delay. Power consumption of an individual transistor decreases by 50%, because active power is CV2f.
Therefore, in every technology generation, the area and power consumption of individual transistors is halved. In other words, if the transistor density doubles, power consumption (with twice the number of transistors) stays the same.
Relation with Moore's law and computing performance
Moore's law says that the number of transistors doubles approximately every two years. Combined with Dennard scaling, this means that performance per joule grows even faster, doubling about every 18 months (1.5 years). This trend is sometimes referred to as Koomey's law. The rate of doubling was originally suggested by Koomey to be 1.57 years, but more recent estimates suggest this is slowing.
Breakdown of Dennard scaling around 2006
The dynamic (switching) power consumption of CMOS circuits is proportional to frequency. Historically, the transistor power reduction afforded by Dennard scaling allowed manufacturers to drastically raise clock frequencies from one generation to the next without significantly increasing overall circuit power consumption.
Since around 2005–2007 Dennard scaling appears to have broken down. As of 2016, transistor counts in integrated circuits are still growing, but the resulting improvements in performance are more gradual than the speed-ups resulting from significant frequency increases. The primary reason cited for the breakdown is that at small sizes, current leakage poses greater challenges and also causes the chip to heat up, which creates a threat of thermal runaway and therefore further increases energy costs.
The breakdown of Dennard scaling and resulting inability to increase clock frequencies significantly has caused most CPU manufacturers to focus on multicore processors as an alternative way to improve performance. An increased core count benefits many (though by no means all – see Amdahl's law) workloads, but the increase in active switching elements from having multiple cores still results in increased overall power consumption and thus worsens CPU power dissipation issues. The end result is that only some fraction of an integrated circuit can actually be active at any given point in time without violating power constraints. The remaining (inactive) area is referred to as dark silicon.