AVX-512 are 512-bit extensions to the 256-bit Advanced Vector Extensions SIMD instructions for x86 instruction set architecture (ISA) proposed by Intel in July 2013, and first implemented in the 2016 Intel Xeon Phi x200 (Knights Landing), and then later in a number of AMD and other Intel CPUs (see list below). AVX-512 consists of multiple extensions that may be implemented independently. This policy is a departure from the historical requirement of implementing the entire instruction block. Only the core extension AVX-512F (AVX-512 Foundation) is required by all AVX-512 implementations.
Besides widening most 256-bit instructions, the extensions introduce various new operations, such as new data conversions, scatter operations, and permutations. The number of AVX registers is increased from 16 to 32, and eight new "mask registers" are added, which allow for variable selection and blending of the results of instructions. In CPUs with the vector length (VL) extension—included in most AVX-512-capable processors (see )—these instructions may also be used on the 128-bit and 256-bit vector sizes. AVX-512 is not the first 512-bit SIMD instruction set that Intel has introduced in processors: the earlier 512-bit SIMD instructions used in the first generation Xeon Phi coprocessors, derived from Intel's Larrabee project, are similar but not binary compatible and only partially source compatible.
Instruction set
The AVX-512 instruction set consists of several separate sets each having their own unique CPUID feature bit; however, they are typically grouped by the processor generation that implements them.
F, CD, ER, PF Introduced with Xeon Phi x200 (Knights Landing) and Xeon Gold/Platinum (Skylake SP "Purley"), with the last two (ER and PF) being specific to Knights Landing. AVX-512 Foundation (F) expands most 32-bit and 64-bit based AVX instructions with the EVEX coding scheme to support 512-bit registers, operation masks, parameter broadcasting, and embedded rounding and exception control, implemented by Knights Landing and Skylake Xeon AVX-512 Conflict Detection Instructions (CD) efficient conflict detection to allow more loops to be vectorized, implemented by Knights Landing and Skylake X AVX-512 Exponential and Reciprocal Instructions (ER) exponential and reciprocal operations designed to help implement transcendental operations, implemented by Knights Landing AVX-512 Prefetch Instructions (PF) new prefetch capabilities, implemented by Knights Landing VL, DQ, BW Introduced with Skylake X and Cannon Lake. AVX-512 Vector Length Extensions (VL) extends most AVX-512 operations to also operate on XMM (128-bit) and YMM (256-bit) registers AVX-512 Doubleword and Quadword Instructions (DQ) adds new 32-bit and 64-bit AVX-512 instructions AVX-512 Byte and Word Instructions (BW) extends AVX-512 to cover 8-bit and 16-bit integer operations IFMA, VBMI Introduced with Cannon Lake. AVX-512 Integer Fused Multiply Add (IFMA) – fused multiply add of integers using 52-bit precision. AVX-512 Vector Byte Manipulation Instructions (VBMI) adds vector byte permutation instructions which were not present in AVX-512BW. 4VNNIW, 4FMAPSIntroduced with Knights Mill. AVX-512 Vector Neural Network Instructions Word variable precision (4VNNIW) – vector instructions for deep learning, enhanced word, variable precision. AVX-512 Fused Multiply Accumulation Packed Single precision (4FMAPS) – vector instructions for deep learning, floating point, single precision. VPOPCNTDQ Vector population count instruction. Introduced with Knights Mill and Ice Lake. VNNI, VBMI2, BITALGIntroduced with Ice Lake. AVX-512 Vector Neural Network Instructions (VNNI) – vector instructions for deep learning. AVX-512 Vector Byte Manipulation Instructions 2 (VBMI2) – byte/word load, store and concatenation with shift. AVX-512 Bit Algorithms (BITALG) – byte/word bit manipulation instructions expanding VPOPCNTDQ. VP2INTERSECT Introduced with Tiger Lake. AVX-512 Vector Pair Intersection to a Pair of Mask Registers (VP2INTERSECT). GFNI, VPCLMULQDQ, VAESIntroduced with Ice Lake. These are not AVX-512 features per se. Together with AVX-512, they enable EVEX encoded versions of GFNI, PCLMULQDQ and AES instructions.
Encoding and features
The VEX prefix used by AVX and AVX2, while flexible, did not leave enough room for the features Intel wanted to add to AVX-512. This has led them to define a new prefix called EVEX.