The Intel Core microarchitecture (provisionally referred to as Next Generation Micro-architecture, and developed as Merom) is a multi-core processor microarchitecture launched by Intel in mid-2006. It is a major evolution over the Yonah, the previous iteration of the P6 microarchitecture series which started in 1995 with Pentium Pro. It also replaced the NetBurst microarchitecture, which suffered from high power consumption and heat intensity due to an inefficient pipeline designed for high clock rate. In early 2004 the new version of NetBurst (Prescott) needed very high power to reach the clocks it needed for competitive performance, making it unsuitable for the shift to dual/multi-core CPUs. On May 7, 2004 Intel confirmed the cancellation of the next NetBurst, Tejas and Jayhawk. Intel had been developing Merom, the 64-bit evolution of the Pentium M, since 2001, and decided to expand it to all market segments, replacing NetBurst in desktop computers and servers. It inherited from Pentium M the choice of a short and efficient pipeline, delivering superior performance despite not reaching the high clocks of NetBurst.
The first processors that used this architecture were code-named 'Merom', 'Conroe', and 'Woodcrest'; Merom is for mobile computing, Conroe is for desktop systems, and Woodcrest is for servers and workstations. While architecturally identical, the three processor lines differ in the socket used, bus speed, and power consumption. The first Core-based desktop and mobile processors were branded Core 2, later expanding to the lower-end Pentium Dual-Core, Pentium and Celeron brands; while server and workstation Core-based processors were branded Xeon.
Features
The Core microarchitecture returned to lower clock rates and improved the use of both available clock cycles and power when compared with the preceding NetBurst microarchitecture of the Pentium 4 and D-branded CPUs. The Core microarchitecture provides more efficient decoding stages, execution units, caches, and buses, reducing the power consumption of Core 2-branded CPUs while increasing their processing capacity. Intel's CPUs have varied widely in power consumption according to clock rate, architecture, and semiconductor process, shown in the CPU power dissipation tables.
Like the last NetBurst CPUs, Core based processors feature multiple cores and hardware virtualization support (marketed as Intel VT-x), and Intel 64 and SSSE3. However, Core-based processors do not have the hyper-threading technology as in Pentium 4 processors. This is because the Core microarchitecture is based on the P6 microarchitecture used by Pentium Pro, II, III, and M.
The L1 cache of the Core microarchitecture at 64 KB L1 cache/core (32 KB L1 Data + 32 KB L1 Instruction) is as large as in Pentium M, up from 32 KB on Pentium II / III (16 KB L1 Data + 16 KB L1 Instruction). The consumer version also lacks an L3 cache as in the Gallatin core of the Pentium 4 Extreme Edition, though it is exclusively present in high-end versions of Core-based Xeons. Both an L3 cache and hyper-threading were reintroduced again to consumer line in the Nehalem microarchitecture.
Roadmap
Technology
While the Core microarchitecture is a major architectural revision, it is based in part on the Pentium M processor family designed by Intel Israel. The pipeline of Core/Penryn is 14 stages long – less than half of Prescott's. Penryn's successor Nehalem has a two cycles higher branch misprediction penalty than Core/Penryn. Core can ideally sustain up to 4 instructions per cycle (IPC) execution rate, compared to the 3 IPC capability of P6, Pentium M and NetBurst microarchitectures. The new architecture is a dual core design with a shared L2 cache engineered for maximum performance per watt and improved scalability.
One new technology included in the design is Macro-Ops Fusion, which combines two x86 instructions into a single micro-operation. For example, a common code sequence like a compare followed by a conditional jump would become a single micro-op. However, this technology does not work in 64-bit mode.
Core can speculatively execute loads ahead of preceding stores with unknown addresses.
Other new technologies include 1 cycle throughput (2 cycles previously) of all 128-bit SSE instructions and a new power saving design. All components will run at minimum speed, raising speed dynamically as needed (similar to AMD's Cool'n'Quiet power-saving technology, and Intel's own SpeedStep technology from earlier mobile processors). This allows the chip to produce less heat, and minimize power use.