Clock skew (sometimes called timing skew) is a phenomenon in synchronous digital circuit systems (such as computer systems) in which the same sourced clock signal arrives at different components at different times due to gate or, in more advanced semiconductor technology, wire signal propagation delay. The instantaneous difference between the readings of any two clocks is called their skew.
The operation of most digital circuits is synchronized by a periodic signal known as a "clock" that dictates the sequence and pacing of the devices on the circuit. This clock is distributed from a single source to all the memory elements of the circuit, which for example could be registers or flip-flops. In a circuit using edge-triggered registers, when the clock edge or tick arrives at a register, the register transfers the register input to the register output, and these new output values flow through combinational logic to provide the values at register inputs for the next clock tick.
Ideally, the input to each memory element reaches its final value in time for the next clock tick so that the behavior of the whole circuit can be predicted exactly. The maximum speed at which a system can run must account for the variance that occurs between the various elements of a circuit due to differences in physical composition, temperature, and path length.
In a synchronous circuit, two registers, or flip-flops, are said to be "sequentially adjacent" if a logic path connects them. Given two sequentially adjacent registers Ri and Rj with clock arrival times at the source and destination register clock pins equal to TCi and TCj respectively, clock skew can be defined as: .
In circuit design
Clock skew can be caused by many different things, such as wire-interconnect length, temperature variations, variation in intermediate devices, capacitive coupling, material imperfections, and differences in input capacitance on the clock inputs of devices using the clock. As the clock rate of a circuit increases, timing becomes more critical and less variation can be tolerated if the circuit is to function properly.
There are two types of clock skew: negative skew and positive skew. Positive skew occurs when the receiving register receives the clock tick later than the transmitting register. Negative skew is the opposite: the transmitting register gets the clock tick later than the receiving register. Zero clock skew refers to the arrival of the clock tick simultaneously at transmitting and receiving register.
Harmful skew
There are two types of violation that can be caused by clock skew. One problem is caused when the clock reaches the first register and the clock signal towards the second register travels slower than output of the first register into the second register - the output of the first register reaches the second register input faster and therefore is clocked replacing the initial data on the second register, or maybe destroying the integrity of the latched data. This is called a hold violation because the previous data is not held long enough at the destination flip-flop to be properly clocked through. Another problem is caused if the destination flip-flop receives the clock tick earlier than the source flip-flop - the data signal has that much less time to reach the destination flip-flop before the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be fixed by increasing the clock period. Positive skew and negative skew cannot negatively impact setup and hold timing constraints respectively (see inequalities below).
Beneficial skew
Where a signal broadly clocks a circuit, the signals/state-transitions it initiates must be stabilized before it signals another set of state transitions -- and that limits the clock's upper frequency. Skew thus decreases the clock frequency at which the circuit will operate correctly. For each source register and destination register connected by a path, the following setup and hold inequalities must be obeyed:
where
T is the clock period, reg is the source register's clock to Q delay, is the path with the longest delay from source to destination, J is an upper bound on jitter, S is the setup time of the destination register represents the clock skew from the source to the destination registers, is the path with the shortest delay from source to destination, H is the hold time of the destination register, is the clock skew to the destination register, and is the clock skew to the source register.