AArch64 or ARM64 is the 64-bit extension of the ARM architecture family. It was first introduced with the Armv8-A architecture. Arm releases a new extension every year.
ARMv8.x and ARMv9.x extensions and features
Announced in October 2011, ARMv8-A represents a fundamental change to the ARM architecture. It adds an optional 64-bit architecture, named "AArch64", and the associated new "A64" instruction set. AArch64 provides user-space compatibility with the existing 32-bit architecture ("AArch32" / ARMv7-A), and instruction set ("A32"). The 16-32bit Thumb instruction set is referred to as "T32" and has no 64-bit counterpart. ARMv8-A allows 32-bit applications to be executed in a 64-bit OS, and a 32-bit OS to be under the control of a 64-bit hypervisor. ARM announced their Cortex-A53 and Cortex-A57 cores on 30 October 2012. Apple was the first to release an ARMv8-A compatible core (Cyclone) in a consumer product (iPhone 5S). AppliedMicro, using an FPGA, was the first to demo ARMv8-A. The first ARMv8-A SoC from Samsung is the Exynos 5433 used in the Galaxy Note 4, which features two clusters of four Cortex-A57 and Cortex-A53 cores in a big.LITTLE configuration; but it will run only in AArch32 mode.
To both AArch32 and AArch64, ARMv8-A makes VFPv3/v4 and advanced SIMD (Neon) standard. It also adds cryptography instructions supporting AES, SHA-1/SHA-256 and finite field arithmetic.
Naming conventions
64 + 32 bit
Architecture: AArch64
Specification: ARMv8-A
Instruction sets: A64 + A32
Suffixes: v8-A
32 + 16 (Thumb) bit
Architecture: AArch32
Specification: ARMv8-R / ARMv7-A
Instruction sets: A32 + T32
Suffixes: -A32 / -R / v7-A
Example: ARMv8-R, Cortex-A32
AArch64 features
New instruction set, A64
Has 31 general-purpose 64-bit registers. Has dedicated zero or stack pointer (SP) register (depending on instruction). The program counter (PC) is no longer directly accessible as a register. Instructions are still 32 bits long and mostly the same as A32 (with LDM/STM instructions and most conditional execution dropped). Has paired loads/stores (in place of LDM/STM). No predication for most instructions (except branches). Most instructions can take 32-bit or 64-bit arguments. Addresses assumed to be 64-bit. Advanced SIMD (Neon) enhanced Has 32 × 128-bit registers (up from 16), also accessible via VFPv4. Supports double-precision floating-point format. Fully IEEE 754 compliant. AES encrypt/decrypt and SHA-1/SHA-2 hashing instructions also use these registers. A new exception system Fewer banked registers and modes. Memory translation from 48-bit virtual addresses based on the existing Large Physical Address Extension (LPAE), which was designed to be easily extended to 64-bit.
Extension: Data gathering hint (ARMv8.0-DGH)
AArch64 was introduced in ARMv8-A and is included in subsequent versions of ARMv8-A. It was also introduced in ARMv8-R as an option, after its introduction in ARMv8-A; it is not included in ARMv8-M.
Instruction formats
The main opcode for selecting which group an A64 instruction belongs to is at bits 25-28.
ARMv8.1-A
In December 2014, ARMv8.1-A, an update with "incremental benefits over v8.0", was announced. The enhancements fell into two categories: changes to the instruction set, and changes to the exception model and memory translation.
Instruction set enhancements included the following:
A set of AArch64 atomic read-write instructions. Additions to the Advanced SIMD instruction set for both AArch32 and AArch64 to enable opportunities for some library optimizations: Signed Saturating Rounding Doubling Multiply Accumulate, Returning High Half. Signed Saturating Rounding Doubling Multiply Subtract, Returning High Half. The instructions are added in vector and scalar forms. A set of AArch64 load and store instructions that can provide memory access order that is limited to configurable address regions. The optional CRC instructions in v8.0 become a requirement in ARMv8.1.
Enhancements for the exception model and memory translation system included the following: